1. Field of the Invention
This invention pertains to the detection of address errors, and more particularly to the detection of address sourcing errors, address transmission errors, and address receiving errors, through the use of redundant address driving devices, parity generation devices, and predetermined stored parity values.
2. Description of the Prior Art
The accuracy of data transmission is a vital element of digital systems. To provide protection against the use of erroneous data, parity is often used to detect possible errors in multiple bit data codes. A parity generation circuit generates a parity bit at the output of a data driving device which represents that either an odd or even number of bits in the multiple bit data codes are at an active logic level. A parity bit is also generated at the input of the data receiving device, which is compared to the parity bit generated at the output of the data driving device. A parity error occurs if the parity bits do not match, which indicates that a data error occurred during transmission of the data.
Parity checking may also be performed on address buses as well as data buses, which provides assurances against faulty addresses being driven on the address bus. The present invention performs address checking by using a parity scheme that checks the validity of the generated address and the validity of the received address. The validity of the generated address is checked by using a master and a slave address driver, each of which simultaneously drive an address. Both the master and the slave address buses are coupled to separate parity generation circuits to generate parity bits for the driven address. The parity bits associated with the master address driver and the parity bits associated with the slave address driver are then each compared with parity bits generated by the address-receiving circuitry. If either the master or the slave address driver parities are inconsistent with the parity generated by the address-receiving circuitry, the circuit will indicate that an error has occurred. This solves the problem which could occur if a single address driver were to generate or output an invalid address.
The validity of the received address is checked through the use of predetermined parity bits which are associated with each unique address that can be generated by the address drivers. The predetermined parity bits are stored in a Random Access Memory (RAM) along with their associated data upon initialization of the system, and are compared to the parity bits generated by each of the address drivers (master and slave). Circuits implementing memory chips to store generated parity are shown in U.S. Pat. No. 4,531,213, by Scheuneman, issued Jul. 23, 1985, and U.S. Pat. No. 4,005,405, by West, issued Jan. 25, 1977. Both of these circuits utilize a memory to store parity bits generated from data being written to the memory. During the writing of data to the memory, one or more parity bits are generated from the data, and stored in the memory along with the data. When this data is to be read, a different parity generation circuit generates one or more parity bits from the data which is read. These two sets of parity bits are then compared, and if equal, no error has occurred.
The present invention checks for errors on an address bus coupled to a memory that is only read and not written to. Therefore, rather than generate parity upon issuance of an address and storing the parity in the memory as in the Scheuneman and West patents, the present invention determines the parity at the time of compiling the information to be stored in the ROM or RAM, and appends the predetermined parity bits with the data to be read. The parity bits associated with a particular address are only calculated once, rather than each time the address is issued. Each address will have a predetermined parity associated with it which is stored with the data to be accessed by that address. The Scheuneman and West patents involve the process of generating parity upon a write, storing the parity in the memory, generating a second parity upon a read of that data, and comparing the two generated parities. The present invention generates one parity which is then compared to the predetermined parity stored in the memory chip. One advantage to using predetermined parities is that the compiler can be programmed to determine these parities, and since compilation occurs prior to the time of system operation, these parity values can be verified to ensure accuracy.
The use of redundant address drivers and predetermined stored address parity bits provides a high degree of error protection for address buses. The use of redundant address drivers allows errors in the transmitting circuitry itself to be detected. The parity bits generated at the address drivers are checked against parity at the receiving circuitry, which provides traditional parity checking of the address signal transmission. The use of predetermined parity bits which are stored in a memory device ensures that the address has been received correctly. This invention therefore provides signal error detection beginning at the transmission circuitry, through the transmission bus, and continuing through the receiving circuitry, rather than only checking for parity errors occurring on the bus during transmission.